SC28L198

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immediately upon enabling the transmitter and persists until a
MR2[7:6] = b 10 selects local loop back mode. In this mode:
character is loaded to the TxFIFO. The Underrun condition will
The transmitter output is internally connected to the receiver
not be a problem as long as the controlling processor keeps up
input.
with the transmitter data flow. The proper operation of this
The transmit clock is used for the receiver.
feature assumes that the transmitter is busy (not underrun) when
The TxD output is held high.
the disable is issued.
The RxD input is ignored.
The last character will be transmitted and RTSN will be reset one
bit time after the last stop bit.
The transmitter must be enabled, but the receiver need not be
enabled.
NOTE: When the transmitter controls the RTSN pin, the meaning of
CPU to transmitter and receiver communications continue
the pin is COMPLETELY changed. It has nothing to do with the
normally.
normal RTSN/CTSN handshaking . It is usually used to mean end
of message and to turn the line around in simplex
The second diagnostic mode is the remote loop back mode,
communications.
selected by MR2[7:6] = b 11. In this mode:
Received data is re clocked and re transmitted on the TxD MR2[4] Clear to Send Control
output.
The state of this bit determines if the CTSN input (I/O0) controls the
The receive clock is used for the transmitter. operation of the transmitter. If this bit is 0, CTSN has no effect on
the transmitter. If this bit is a 1, the transmitter checks the state of
Received data is not sent to the local CPU, and the error status
conditions are inactive. CTSN each time it is ready to begin sending a character. If it is
1999 Jan 14 20
Philips Semiconductors Product specification
Octal UART for 3.3V and 5V supply voltage SC28L198
asserted (low), the character is transmitted. If it is negated (high), MR2[1:0] Stop Bit Length Select
the TxD output remains in the marking state and the transmission is This field programs the length of the stop bit appended to the
delayed until CTSN goes low. Changes in CTSN, while a character transmitted character. Stop bit lengths of 9/16, 1, 1.5 and 2 bits can
is being transmitted, do not affect the transmission of that character. be programmed for character lengths of 6, 7, and 8 bits. For a
This feature can be used to prevent overrun of a remote receiver. character length of 5 bits, 1, 1.5 and 2 stop bits can be programmed.
In all cases, the receiver only checks for a mark condition at the
MR2[3:2] RxINT control field
center of the first stop bit position (one bit time after the last data bit,
Controls when interrupt arbitration for a receiver begins based on
or after the parity bit if parity is enabled). If an external 1X clock is
RxFIFO fill level. This field allows interrupt arbitration to begin when
used for the transmitter, MR2[1] = 0 selects one stop bit and MR2[1]
the RxFIFO is full, 3/4 full, 1/2 full or when it contains at least 1
= 1 selects two stop bits to be transmitted.
character.
Table 6. RxCSR and TxCSR Receiver and Transmitter Clock Select Registers
Both registers consist of single 5 bit field that selects the clock source for the receiver and transmitter, respectively. The unused bits in this
register read b 111. The baud rates shown in the table below are based on the x1 crystal frequency of 3.6864MHz. The baud rates shown
below will vary as the X1 crystal clock varies. For example, if the X1 rate is changed to 7.3728 MHz all the rates below will double.
Bits 7:5 Bits 4:0
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Reserved Transmitter/Receiver Clock select code, (see Clock Mux Table below)
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Table 7. Data Clock Mux
CCLK maximum rate is 8MHz. Data clock rates will follow exactly the ratio of CCLK to 3.6864MHz.
Clock selection, Clock selection,
Clock Select Code
Clock Select Code
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CSR (4:0)
CCLK = 3.6864 MHz CCLK = 3.6864 MHz
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00000 BRG 50 10000 BRG 19.2K
00001 ��
BRG 75 10001 BRG 28.8K
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00010 BRG 150 10010 BRG 38.4K
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00011 BRG 200 10011 BRG 57.6K
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00100 BRG 300 10100 BRG 115.2K
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00101 BRG 450 10101 BRG 230.4K
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00110 ��
BRG 600 10110 GIN0
00111 BRG 900 10111 GIN1
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01000 BRG 1200 11000 BRG C/T 0
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01001 BRG 1800 11001 BRG C/T 1
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01010 BRG 2400 11010 Reserved
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01011 BRG 3600 11011 I/O2 rcvr, I/O3 xmit 16x
01100 BRG 4800 11100 I/O2 rcvr, I/O3 xmit 1x
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01101 BRG 7200 11101 Reserved
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01110 BRG 9600 11110 Reserved
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01111 BRG 14.4K 11111 Reserved
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1999 Jan 14 21
Philips Semiconductors Product specification
Octal UART for 3.3V and 5V supply voltage SC28L198
be true before break begins). The transmitter must be
Table 8. CR Command Register
enabled to start a break.
00111 Stop break. The TxD line will go high (marking) within two
CR is used to write commands to the Octal UART.
bit times. TxD will remain high for one bit time before the
Bits 7:3 Bit 2 Bit 1 Bit 0
next character, if any, is transmitted.
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01000 Assert RTSN. Causes the RTSN output to be asserted
Channel Com-
Lock TxD and�
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(low).
mand codes
RxFIFO en- Enable Tx Enable Rx
01001 Negate RTSN. Causes the RTSN output to be negated [ Pobierz całość w formacie PDF ]

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